The present invention relates generally to a semiconductor circuit, and in particular to an address decoder, and an active control circuit, and a semiconductor memory including the same.
Semiconductor memory may include, for example, a high bandwidth memory (HBM), having a structure in which a plurality of dies are stacked and coupled through a through-electrode, and thus the number of input/output (I/O) units is increased and the bandwidth is increased.
The semiconductor memory may receive an address and a command in an integrated form from an exterior device through an address pin.
Since the semiconductor memory includes a plurality of stacked dies, there is a need for an address processing method for efficiently operating the plurality of stacked dies, by considering circuit area, signal processing timing margin, and the like.